PROF. RAJENDRA KUMAR NAGARIA
Professor
Department of Electronics & Communication Engineering
Motilal Nehru National Institute of Technology Allahabad, Prayagraj, India-211004
E-mail: rkn[at]mnnit[dot]ac[dot]in
Telephone: +91-532-2271464(O) +91-532-2271813(R)
Thesis Supervised
| S.No | Research Topic | Name of Student | Completion/Registration Year | Ph.D. Completed: |
|---|---|---|---|
| 1 | Performance analysis on PAPR reduction techniques for power efficiency improvement in OFDM systems | Pankaj Kumar Sharma | 2011 |
| 2 | Performance Evaluation of Survivable WDM Mesh Networks | Baibaswata Mohapatra | 2011 |
| 3 | Studies of Current Feedback Amplifier based circuits suitable for analog signal processing and VLSI design | Rakesh Kumar Singh | 2012 |
| 4 | Performance evaluation of high speed low power CMOS full adder circuits for low voltage VLSI design | Subodh Wairya | 2012 |
| 5 | Performance evaluation of Domino CMOS circuits for low voltage VLSI Design | Amit Kumar Pandey | 2014 |
| 6 | Studies of Adiabatic Logic Circuits suitable for energy aware and performance efficient VLSI applications | Shipra Upadhyay | 2015 |
| 7 | Studies of Low Power VLSI Design Approaches suitable for Energy Efficient Nanoscale Circuits | Sankit Ramkrishna Kassa | 2016 |
| 8 | Studies of High-Speed Low Power CMOS Double-Tail Dynamic Comparators Suitable for Analog/Mixed-Signal Processing | Avaneesh Kumar Dubey | 2019 |
| 9 | Studies of Low-Voltage Low-Power MOSFET-Only Subthreshold Voltage Reference Circuits Suitable for Analog Signal Systems | Pratosh Kumar Pal | 2019 |
| 10 | Studies of Leakage and Variation Tolerant Wide Fan-in OR Logic Domino Circuits | Ankur Kumar | 2020 |
| 11 | Studies of Low-Voltage High-Speed CMOS Double-Tail Dynamic Comparators Suitable for Analog/Mixed-Signal Applications | Vikrant Varshney | 2020 |
| 12 | Efficient Anchor-based Angular Routing Protocols for 3-Dimensional Wireless Sensor Networks | Naveen Kumar Gupta | 2020 |
| 13 | Studies of Electronically Tunable CMOS Current Controlled Conveyor Based Active Building Blocks Suitable for Analog Signal Processing | Priyanka Singh | 2022 |
| 14 | FABRICATION AND CHARACTERIZATION OF TUNGSTEN DI SELENIDE (WSe2) BASED PHOTODETECTORS | Tulika Bajpai | 2025 | Ph.D. Ongoing |
| 1 | Analog/ Mixed-Mode VLSI Circuits | Vikas Tiwari | 2020 |
| 2 | Design and Performance Analysis of High-Speed Low-Power CMOS Double-Tail Dynamic Comparator for SAR ADC | Vikas Tiwari | 2020 |
| 3 | Study of Junction-Less Tunnel FET Devices Suitable for BioSensor Applications | Archana Verma | 2022 |
| 4 | Analog/Mixed Mode Circuit Design | Vinay Kumar | 2024 | M.Tech Students |
| 1 | Calibration software for interfacing devices through GPIB using IBM PC-AT | Lalit Mohan Srivastava | 2000 |
| 2 | CFA based universal filters suitable for analog signal processing | InduPrabha Singh | 2006 |
| 3 | Active contours without re-initialization for image segmentation | Harikishore S | 2007 |
| 4 | Performance Enhancement and Comparison of CMOS Current Feedback Operational Amplifier | Gopi Krishna Maringanti | 2008 |
| 5 | Design and simulation of mixed gate diffusion input full adder topology for high performance arithmetic circuits | Adarsh Kumar Agrawal | 2009 |
| 6 | Comparative performance analysis of various CMOS design techniques for XOR-XNOR circuits | Shiv Shankar Mishra | 2009 |
| 7 | Design and simulation of low power full adder cell for low voltage | V. Narender | 2010 |
| 8 | Energy efficient full adder cells based on majority logic function | Pankaj Kumar Tripathi | 2011 |
| 9 | Implementation of 5 bit Array Multiplier using high performance 1 bit full Adder for Low Power Applications | Vishant | 2012 |
| 10 | MOS-diode based adiabatic logic circuits for low power application | Prashant Shekhar | 2012 |
| 11 | Comparative Study on Keeper Design Approach for Low Power and High Speed Domino Logic Circuits | Pushpa Rani | 2012 |
| 12 | Design and Implementation of Fully Static Domino Styles Suitable for Low-Power Wide Fan-in Logic Circuits | Y. Krishna Mohan | 2013 |
| 13 | Design and Simulation of Dynamic Circuit Using Footed Diode Domino Logic For High Performance VLSI Applications | Sujeet Kumar | 2013 |
| 14 | Comparative Study of Double Gate SOI FinFET and Trigate Bulk MOSFET for VLSI Design | Sanchit Singhal | 2013 |
| 15 | Delay optimization of Boosted CMOS Differential Logic | Jyotsana Singh | 2014 |
| 16 | Study on High Performance Transconductor Suitable for Low Power gm-C Filters | Vineet Jaiswal | 2014 |
| 17 | Simulation Study of ZnO based Thin Film Transistor | Vinay Kumar | 2014 |
| 18 | Design and Simulation of Ground Pane FinFET (GP-FinFET) Suitable for Low Leakage Circuits | Ashish Kumar Yadav | 2015 |
| 19 | Device Simulation and Performance Evaluation of Bulk FinFET | Suraj G. Dhongade | 2015 |
| 20 | Performance Analysis of Footed Pseudo Dynamic Buffer Scheme for Low Power VLSI Circuits | Thota Ravi Sankar | 2016 |
| 21 | Logical Effort Approach of Delay and Dynamic Power Estimation for Low Power VLSI Circuits | Ankur Kumar | 2016 |
| 22 | Design and analysis of low voltage low power high speed dynamic comparator for analog to digital converter | Rahul Jain | 2017 |
| 23 | Performance evaluation of low power high speed hybrid full adder circuit | Vivek Saraswat | 2017 |
| 24 | Reduction of delay variation in Domino Logic gates using keeper circuit approach | Shreyashi | 2017 |
| 25 | Performance Analysis of Low Power Symmetric SRAM Cell | Manav Bansal | 2018 |
| 26 | Design Consideration of a Symmetric Pass Gate Adiabatic Logic Suitable for Energy Efficient Low Power Circuits | Jyoti Agrawal | 2018 |
| 27 | Physical Implementation of a SoC Block Using Low Power Techniques | Anju Ashra | 2019 |
| 28 | An FPGA-Based Soft-Core Micro-Architecture with Optimized Instruction Set Suitable for Mixed-Signal Processing | Patil Ashish Vilas | 2019 |
| 29 | Architectural Modification of Fetch Engine in Mobile Display Sub-System for Improving Area & Power | Anil Mishra | 2020 |
| 30 | Designing of muxed output ring Oscillator (MORO) Test chip for the parameter verification of devices under Test | Avinash Mishra | 2020 |
| 31 | Improving the Electrical Characteristics of Nanoscale Triple-Gate Junctionless FinFET Using Gate Oxide Engineering | Arunita Mukherjee | 2021 |
| 32 | Fin Shape Influence on Analog and RF Performance of Junctionless Accumulation-Mode Bulk FinFETs | Vaghela Mihir Atulbhai | 2021 |
| 33 | Study of High Speed Low Power Sigma-Delta Analog to Digital Converter | Virat Mathur | 2022 |
| 34 | Study of High Performance Low Power Successive Approximation Register Analog to Digital Converter | Kumar Shubham | 2022 |
| 35 | Area and Energy Efficient Switching Scheme for Successive Approximation Register (SAR) ADC | Chahat Batra | 2023 |
| 36 | Study of High Speed Low Power Dynamic Comparator for CMOS Mixed Signal Applications | Ankur Goyal | 2023 |
| 37 | Phase Error Compensation Technique for fast-locking PLL | Apoorav Mahajan | 2024 |
| 38 | PERFORMANCE ANALYSIS OF A SEMI-SYNCHRONOUS SAR ADC USING DLL | ASWATHI KRISHNAN | 2024 |
| 39 | STUDY ON CURRENT FEEDBACK AMPLIFIER BASED FOUR QUARDANT ANALOG MULTIPLIER / DIVIDER CIRCUIT SUITABLE FOR ANALOG SIGNAL PROCESSING | GOURU HEMANTH | 2024 |
| 40 | Design and Implementation of Digital Comparator Circuit Using Quantum-dot Cellular Automata | ANURAG GUPTA | 2025 |