Prof. Amit Dhawan
Professor
Department of Electronics & Communication Engineering
Motilal Nehru National Institute of Technology Allahabad, Prayagraj, India-211004
E-mail: dhawan[at]mnnit[dot]ac[dot]in
Telephone: 05322271451(O)
Thesis Supervised
| S.No | Research Topic | Name of Student | Completion/Registration Year | Ph.D. Completed: |
|---|---|---|---|
| 1 | Linear Matrix Inequality Based Criteria for Optimal Guaranteed Cost Control of Uncertain Two-Dimensional Discrete Systems | Dr. Manish Tiwari | 2012 |
| 2 | Linear Matrix Inequality Based Criteria for Non-Fragile Robust Optimal Guaranteed Cost Control of Two-Dimensional Discrete Uncertain Systems | Dr. Akshata Tandon | 2017 |
| 3 | LMI Approach to Robust Optimal H-infinity Control for Uncertain 2-D Discrete Delayed Systems | Dr. Arun Kumar Singh | 2018 | Ph.D. Ongoing |
| 1 | Signal Processing | Mr. Akhilesh Kumar Ravat | 2017 |
| 2 | Signal Processing | Mr. Sanjiv Kumar Gupta | 2019 |
| 3 | Signal Processing | Mr. Nilesh Kumar Yadav | 2020 | M.Tech Students |
| 1 | Application of Kalman Filtering in tracking a moving object using the background subtraction method | Mr. Tarun Gupta | 2020 |
| 2 | Development and Application on Predictive Controller | Mr. Ankur Mittal | 2020 |
| 3 | Exploring Noise Reduction Methodologies in Heart Attack Prediction | Ms. Pratiksha Gupta | 2019 |
| 4 | Image Compression and Gamma Correction using Wavelet Transform | Mr. Salman Latif | 2019 |
| 5 | Low Complexity Algorithm for Reducing Memory Requirement in JPEG2000 Images | Ms. Roopam Seth | 2018 |
| 6 | Realization of Fractional Order High Pass Filter using Switched Capacitor | Mr. Shailesh Maurya | 2017 |
| 7 | Noise Cancellation using Adaptive Filter | Mr. Akhilesh Kr. Ravat | 2017 |
| 8 | Non Uniform 12-Band FIR Digital Filter Bank Based on Frequency Response Masking Technique for Hearing Aid | Mr. Yeramala Suresh | 2016 |
| 9 | Power Reduction in DSP Processor for Multimedia Applications | Mr. Amarendra Kr. Tripathi | 2016 |
| 10 | Realization of a DA-Based Reconfigurable FIR Digital Filter by FPGA and ASIC | Mr. Bikrant Kumar | 2015 |
| 11 | Performance Analysis of Evolutionary Algorithms for Analog Active Filter Design | Mr. K. Ashok Vardhan | 2015 |
| 12 | Digital Chebyshev Filter For Subtracting Noise from Low Magnitude Surface Electromyogram | Mr. Gaurav Upadhyay | 2014 |
| 13 | Analysis of COSH Window Function and its Applications | Mr. Ravi Rastogi | 2013 |
| 14 | Digital Parametric Equalizer design for Analog Modeling | Mr. Satyendra Kr. Kushwaha | 2013 |
| 15 | Analysis of Impulse Response of Fractional Order Filters | Mr. Deepak Kr. | 2013 |
| 16 | Single and Double Notch IIR and FIR Filter Design with Narrow Rejection Bandwidth | Ms. Anita Kodap | 2012 |
| 17 | A Comparison Between Improved Impulse Invariance Method and Bilinear Transformation Method for the design of IIR Digital Filter | Mr. Ashok Kr. | 2012 |
| 18 | Wavelet Based Color Image Compression | Mr. Ramesh Kr. Bhukya | 2011 |
| 19 | Multiplication Mode Current Conveyor, An Analog Multiplier | Mr. Sandeep Kr. Kesharwani | 2010 |
| 20 | A Novel High-Speed Multiplexer-Based Full Adder | Mr. Chaitanya Kommu | 2009 |
| 21 | High-Speed Architecture of the Whirlpool Hash Function | Mr. A. V. B. Reddy | 2009 |
| 22 | Multi-Threshold CMOS Design for Low Power Digital Circuits | Mr. Hemantha S | 2008 |
| 23 | Design of a flexible transposition free VLSI of 2-D and 3-D DFT using systolic structure | Mr. Sakhamuri Sasidhara Rao | 2007 |
| 24 | A Novel Technique for Realizing on Line Linear Phase IIR Filters | Mr. Satyabrata Das | 2005 |
| 25 | Micro-Mobility Mechanism for Smooth Handoffs in an Integrated ad-hoc and Cellular IPv6 Network under High-speed movement | Mr. Selvaraju | 2005 |
| 26 | SMPP Protocol Implementation over CDMA Technology | Mr. Sunder Singh | 2005 |
| 27 | Signed binary addition circuitry with inherent even and odd parity outputs. | Mr. Ajay Singh | 2004 |
| 28 | Pass Transistor logic technique for the synthesis of digital circuits. | Mr. Sivam Prasad Tera | 2004 |
| 29 | Spectral Technique for Built in Self-Test. | Mr. Aditya Chaudhary | 2004 |
| 30 | Leakage Power Reduction in CMOS Circuit Using DUAL THRESHOLD Techniques. | Mr. Jagateswar Patra | 2004 |
| 31 | Test Set Compaction in Combinational Circuits | Mr. Narendra Singh | 2004 |
| 32 | Design of Linear Phase FIR Filter Using PARKS-McCLELLAN Algorithm | Mr. Mohammad Rashid Ansari | 2003 |
| 33 | Performance Analysis of Multiple Notch Filter Design | Mr. Indhra Deo Kumar | 2003 |
| 34 | IIR Filter Design | Mr. Sudheer Kumar Gummadi | 2003 |
| 35 | Performance Analysis of FIR Filter Design | Mr. Raj Kumar Chaurasia | 2003 |
| 36 | The Performance Evaluation of Low-Voltage Low-Power CMOS Full Adder | Mr. Mahammad Rafi | 2002 |
| 37 | Reducing the PBF Calculation Stages in Stack Filters Using Sample Selection Technique | Mr. Pramod Kumar Gupta | 2001 |