Dr. Aditya Anshul


Dr. Aditya Anshul

Assistant Professor
Department of Computer Science & Engineering
Motilal Nehru National Institute of Technology Allahabad, Prayagraj, India-211004
E-mail: adityaanshul[at]mnnit[dot]ac[dot]in
Telephone: 9968398036(O) 9968398036(M)

Research Publications


Book Chapter:

A. Anshul, R. Chaurasia, A. Sengupta ”Securing Hardware Coprocessors against Piracy using Biometrics for Secured IoT systems”, IET Book, ”Artificial Intelligence for Biometrics and Cybersecurity”, 2023, Chapter DOI:10.1049/PBSE020E-ch8.
A. Anshul, A. Sengupta, ”Role of Consumer Technology and Connected Electronic Devices on SCM: A Discussion on its Usages, Impact, and Challenges”, UTHM Book, ”Evolution of Information, Communication and Computing System”, 4(1), 1-11, 2023.
A. Sengupta, A. Anshul, ”Machine Learning-based Detection of HLS Trojans”, IET Book, ”High-Level Synthesis Hardware Trojan Attacks and Countermeasures”, Accepted, To appear in 2026.
A. Sengupta, A. Anshul, ”HLS Based Fingerprinting”, IET Book, ”High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”, 2024, Chapter DOI:10.1049/PBCS084E-ch7.
A. Sengupta, A. Anshul, ”High Level Synthesis based Watermarking using Crypto-Chain Signature Framework”, IET Book, ”High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”, 2024, Chapter DOI: 10.1049/PBCS084E-ch6.
A. Sengupta, A. Anshul, ”High Level Synthesis based Watermarking using Multi-modal Biometric”, IET Book, ”High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”, 2024, Chapter DOI: 10.1049/PBCS084E-ch5.
A. Sengupta, A. Anshul, ”HLS based Mathematical Watermarks for Hardware Security and Trust”, IET Book, ”High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”, 2024, Chapter DOI: 10.1049/PBCS084E-ch4.
A. Sengupta, A. Anshul, ”High-Level Synthesis based Watermarking using Protein Molecular Biometric with Facial Biometric Encryption”, IET Book, ”High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”, 2024,Chapter DOI: 10.1049/PBCS084E-ch2.
A. Sengupta, A. Anshul, ”Palmprint Biometrics Vs. Fingerprint Biometrics Vs. Digital Signature using Encrypted Hash: Qualitative and Quantitative Comparison for Security of DSP coprocessors”, IET Book, ”Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors”, 2023,Chapter DOI: 10.1049/PBCS080E-ch6.
A. Sengupta, A. Anshul, ”Secured Design Flow using Palmprint Biometrics, Steganography and PSO for DSP coprocessors”, IET Book, ”Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors”, 2023,Chapter DOI: 10.1049/PBCS080E-ch7.
• A. Sengupta, A. Anshul, ”Taxonomy of Hardware Security Methodologies: IP Core Protection and Obfuscation”, IET Book, ”Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors”, 2023,Chapter DOI: 10.1049/PBCS080E-ch9.

Journals:

M. Rathor, A. Anshul, A. Sengupta, ”Securing Reusable IP Cores using Voice Biometric based Watermark”, IEEE Transactions on Dependable and Secure Computing, vol. 21, no. 4, pp. 2735-2749, July-Aug. 2024, DOI: 10.1109/TDSC.2023.3315780, (Impact Factor: 7.5).
A. Sengupta, R. Chaurasia and A. Anshul, ”Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 6, pp. 826-839, June 2023, DOI: 10.1109/TVLSI.2023.3265559, (Impact Factor: 3.1).
A. Sengupta, A. Anshul, and N. Bhui. 2026. SHiELD: Functional Obfuscation of DSP Cores Using HLS Based One-Way Random Function and Reconfigurable Composite Switching Obfuscation Cells. ACM Trans. Embed. Comput. Syst. 25, 2, Article 32 (March 2026), 22 pages. https://doi.org/10.1145/3793677, (Impact Factor: 2.6).
A. Anshul, A. Sengupta, HLS Trojan Detection Using Machine Learning Technique,IEEE Embedded Systems Letters, Early Access Article, DOI: 10.1109/LES.2025.3614187, (Impact Factor: 2.0).
A. Anshul, A. Sengupta, PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis,Elsevier Expert Systems with Applications, Volume 223, 2023, 119927, DOI: 10.1016/j.eswa.2023.119927, (Impact Factor: 7.5).
A. Anshul, A. Sengupta ”Exploration of Optimal Crypto-Chain Signature Embedded Secure JPEG-CODEC Hardware IP during High Level Synthesis”, Elsevier Journal on Microprocessors and Microsystems, Volume 102, October 2023, 104916, DOI: 10.1016/j.micpro.2023.104916, (Impact factor: 2.6).
A. Anshul and A. Sengupta, ”A Survey of High Level Synthesis Based Hardware Security Approaches for Reusable IP Cores,” IEEE Circuits and Systems Magazine, vol. 23, no. 4, pp. 44-62, Fourthquarter 2023, DOI: 10.1109/MCAS.2023.3325607, (Impact Factor: 3.5).
M. Rathor, A. Sengupta, R. Chaurasia and A. Anshul, ”Exploring Handwritten Signature Image Features for Hardware Security,” IEEE Transactions on Dependable and Secure Computing, vol. 20, no. 5, pp. 3687-3698, 1 Sept.-Oct. 2023, DOI: 10.1109/TDSC.2022.3218506, (Impact Factor: 7.5).
A. Sengupta and A. Anshul, ”Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework,” IEEE Access, vol. 12, pp. 47494-47507, 2024, doi: 10.1109/ACCESS.2024.3382202, (Impact Factor; 3.4).
A. Sengupta and A. Anshul, "A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking Approaches," IEEE Design & Test, vol. 41, no. 6, pp. 70-83, Dec. 2024, doi: 10.1109/MDAT.2024.3435056, (Impact factor: 1.9).
A. Sengupta, N. Bhui and A. Anshul, "High-Level Synthesis-Based Forensic Watermarking of Hardware IPs Using IP Vendor’s DNA Signature," IEEE Embedded Systems Letters, vol. 18, no. 1, pp. 19-22, Feb. 2026, doi: 10.1109/LES.2025.3566674, (Impact factor: 2.0).
A. Sengupta, A. Anshul, V. Chourasia and N. Kumar, ”M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs,” IEEE Embedded Systems Letters, vol. 16, no. 4, pp. 497-500, Dec. 2024, doi: 10.1109/LES.2024.3416422, (Impact factor: 2.0).
R. Chaurasia, A. Anshul, A. Sengupta and S. Gupta, ”Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems,” IEEE Consumer Electronics Magazine, vol. 11, no. 5, pp. 73-80, 1 Sept. 2022, doi: 10.1109/MCE.2022.3153276, (Impact Factor: 4.1).
A. Sengupta, A. Anshul, V. Chourasia and N. Bhui, ”Security Vulnerability (Backdoor Trojan) During Machine Learning Accelerator Design Phases,” IEEE IT Professional, vol. 27, no. 1, pp. 65-72, Jan.-Feb. 2025, doi: 10.1109/MITP.2024.3519632, (Impact Factor: 2.6).
A. Sengupta, A. Anshul, Secure hardware IP of GLRT cascade using color interval graph based embedded fingerprint for ECG detector. Nature Scientific Reports, 14, 13250 (2024), doi: 10.1038/s41598-024-635337, (Impact Factor: 3.8).
A. Sengupta, N. Bhui, A. Anshul, V. Chourasia, Bio-mimicking DNA fingerprint profiling for HLS watermarking to counter hardware IP piracy. Nature Scientific Reports, 14, 22413 (2024). https://doi.org/10.1038/s41598024-73119-y, (Impact Factor: 3.8).
A. Sengupta, A. Anshul, Exploring low overhead fingerprint biometric watermark for loop pipelined hardware IPs during behavioral synthesis, Elsevier Journal of Information Security and Applications, Volume 90, 2025, 104041, doi: 10.1016/j.jisa.2025.104041, (Impact Factor: 3.7).
A. Sengupta, A. Anshul, R. Chaurasia ”Exploration of Optimal Functional Trojan-Resistant Hardware Intellectual Property (IP) Core Designs during High Level Synthesis”, Elsevier Journal on Microprocessors and Microsystems, Volume 103, November 2023, 104973, doi.org/10.1016/j.micpro.2023.104973, (Impact Factor: 2.6).
M. Rathor, A. Anshul, K Bharath, R. Chaurasia, A. Sengupta, Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores, Elsevier Computers and Electrical Engineering, Volume 105, 2023, 108476, doi: 10.1016/j.compeleceng.2022.108476, (Impact factor: 4.0).
A. Sengupta, V. Chourasia, N. Bhui, A. Anshul, ”Hardware Watermarking of Transient Fault-Detectable IP Designs using Multivariate Encoded HLS Scheduling based Multi-Modal Security Methodology”, IET Computers and Digital Techniques, Accepted, 2025, doi: 10.1049/cdt2/5926846, (Impact factor: 0.8).
A. Sengupta, A. Anshul, Hardware Security of Image Processing Cores Against IP Piracy Using PSO-Based HLS-Driven Multi-Stage Encryption Fused with Fingerprint Signature. SN COMPUT. SCI. 5, 941 (2024), doi.org/10.1007/s42979-024-03255-9.
A. Sengupta, A. Anshul, A. K. Singh, Hardware security against IP piracy using secure fingerprint encrypted fused amino-acid biometric with facial anthropometric signature, Elsevier Journal of Microprocessors and Microsystems, Volume 112, 2025, 105131, doi.org/10.1016/j.micpro.2024.105131, (Impact factor: 2.6).

Conference Proceedings:

A. Anshul, A. Sengupta, V. Chourasia ”Secure Optimized Hardware IP Design Using Key-Driven Hash Slicing Based HLS Watermarking Integrated with Krill-Herd DSE”, 2025 IEEE 38th International System-on-Chip Conference (SOCC), Dubai, United Arab Emirates, 2025, pp. 1-6, DOI: 10.1109/SOCC66126.2025.11235474.
A. Sengupta, R. Chaurasia and A. Anshul, ”Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller’s Fingerprint Encrypted Amino Acid Biometric Sample,” 2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Tianjin, China, 2023, pp. 1-6, DOI: 10.1109/AsianHOST59942.2023.10409476.
A. Anshul and A. Sengupta, ”Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO,” 2023 IEEE International Symposium on Smart Electronic Systems (iSES), Ahmedabad, India, 2023, pp. 135-140, DOI: 10.1109/iSES58672.2023.00037. Note: Awarded Springer Nature Best Paper Award.
A. Anshul, K. Bharath and A. Sengupta, ”Designing Low Cost Secured DSP Core using Steganography and PSO for CE systems,” 2022 IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, 2022, pp. 95-100, DOI: 10.1109/iSES54909.2022.00030.
A. Anshul and A. Sengupta, ”IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints,” 2022 IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, 2022, pp. 83-88, DOI: 10.1109/iSES54909.2022.00028.
A. Sengupta, A. Anshul, S. Thakur and C. Kothari, ”Fusing IP vendor Palmprint Biometric with Encoded Hash for Hardware IP Core Protection of Image Processing Filters,” 2023 International Conference on Microelectronics (ICM), Abu Dhabi, United Arab Emirates, 2023, pp. 218-221, DOI: 10.1109/ICM60448.2023.10378937.
A. Sengupta, A. Anshul, C. Kothari and S. Thakur, ”Secured and Optimized Hardware Accelerators using Key-Controlled Encoded Hash Slices and Firefly Algorithm based Exploration,” 2023 International Conference on Microelectronics (ICM), Abu Dhabi, United Arab Emirates, 2023, pp. 149152, DOI: 10.1109/ICM60448.2023.10378911.
A. Sengupta, V. Chourasia, A. Anshul, ”HLS Scheduling Driven Encoded Watermarking for Secure Convolutional Layer IP Design in CNN”, 2024 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan), Taichung, Taiwan, 2024, pp. 587-588, DOI: 10.1109/ICCETaiwan62264.2024.10674266.
A. Sengupta, V. Chourasia, A. Anshul, N. Kumar, ”Robust Watermarking of Loop Unrolled Convolution Layer IP Design for CNN using 4-variable Encoded Register Allocation”, 2024 International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan), Taichung, Taiwan, 2024, pp. 589-590, DOI: 10.1109/ICCE-Taiwan62264.2024.10674385.
A. Sengupta, A. Anshul, N. Bhui ”Timer-driven HLS Trojan attack on Medical System Hardware”, 2025 IEEE International Symposium on Smart Electronic Systems (iSES), Accepted, Jaipur, India 2025.
A. Sengupta, A. Anshul, N. Bhui ”Embedding Steganography Digest using Shannon’s Decomposition for Hardware Security against False IP Ownership Attack”, 2025 IEEE International Symposium on Smart Electronic Systems (iSES), Accepted, Jaipur, India 2025. Note: Awarded Best Paper Award (Winner) out of 217 submissions.
A. Sengupta and A. Anshul, ”Key-Driven Multi-Layered Structural Obfuscation of IP cores using Reconfigurable Obfuscator based Network Challenge and Switch Control Logic,” 2023 IEEE International Symposium on Smart Electronic Systems (iSES), Ahmedabad, India, 2023, pp. 141-146, DOI: 10.1109/iSES58672.2023.00038.
A. Sengupta, A. Anshul and V. Chourasia, ”HLS Based Hardware Watermarking Using IP Seller’s Superimposed Facial Anthropometric Features,” 2024 IEEE International Symposium on Smart Electronic Systems (iSES), New Delhi, India, 2024, pp. 110-115, doi: 10.1109/iSES63344.2024.00032.