Dr. SANJEEV RAI
Associate Professor
Department of Electronics & Communication Engineering
Motilal Nehru National Institute of Technology Allahabad, Prayagraj, India-211004
E-mail: srai[at]mnnit[dot]ac[dot]in
Telephone: 05322271471(O) 09621781174(M)
Thesis Supervised
| S.No | Research Topic | Name of Student | Completion/Registration Year | Ph.D. Completed: |
|---|---|---|---|
| 1 | Performance Enhancement and Analysis of Modified Structure based Junction-less double gate MOSFET | Abhinav | 2017 |
| 2 | Modeling, Analysis and Physics of Threshold voltage variation for Advanced Nano MOSFETs | Yashu Swami | 2019 |
| 3 | Modeling, Analysis and Study of Self-Heating Effect on Selective Buried Oxide Junction-less Transistors | Amrish Kumar | 2021 | Ph.D. Ongoing |
| 1 | Signal Processing | Sonelal Prajapati | 2017 |
| 2 | Negative Capacitance Based Junction-less Transistors | Manish Kumar Rai | 2018 |
| 3 | Effect on Performance Parameters of Stained MOSFETs | Shubham Verma | 2020 | M.Tech Students |
| 1 | Performance Enhancement of 1-Bit Conventional CMOS Full Adder Using MTCMOS Design | Muraleedhara Patro | 2010 |
| 2 | A Low Power Variation Tolerant Sub-Threshold 5-T SRAM Cell Design | Mr. Subhash Kumar Mishra | 2010 |
| 3 | Design And Analysis of Two Low-Power Source Coupled Logic Structures | Abhinav | 2011 |
| 4 | Design And Optimization of Triple Gate Finfet | Jyotsna Sahu | 2012 |
| 5 | Power-Delay Reduction Techniques For Ultra-Low-Power Sub-Threshold SCL Circuits | Sumit Vyas | 2012 |
| 6 | Design of Low Power High Speed CMOS Cell Structure Based on Adiabatic Switching Principle | Govind Krishna Pal | 2012 |
| 7 | Design And Analysis of ULL Circuits For High-Performance Finfet Applications | Pushpa Giri | 2013 |
| 8 | Layout Based ESD Analysis And Verification For SoC Designs | Ms. Shilpa Singh | 2013 |
| 9 | Comparative Study of Fault Modeling For SG-Mode And LP-Mode Inverter | Archana Verma | 2013 |
| 10 | Comparative Analysis of Junctionless Transisor With Different Substrate Material | Anjali Priya | 2014 |
| 11 | Comparative Analysis of Fractional And Integer Second Order Filter | Vishal Kumar Pandey | 2014 |
| 12 | Dielectric Pocket Junctionless Cylindrical Double Surrounding Gate (DP-JLDSG) MOSFET For Low Power Application | Manoj Kumar | 2015 |
| 13 | An Ultra Thin Body Nanoscale Dual Material Double Gate SOI MOSFET | Anil Kumar | 2015 |
| 14 | Analytical Modeling And Analysis Of Junctionless Double Gate (JLDG) MOSFET For Analog/RF Applications | Nirmal Chandra Roy | 2015 |
| 15 | Ultralow Power Junctionless DG MOSFET | Praveen Kumar | 2015 |
| 16 | Investigation Of Zero Temperature Coefficient (ZTC) Bias Point For Symmetrical And Asymmetrical Dual Material Double Gate (DMDG) Mosfets | Yogeswar Nath Pandey | 2016 |
| 17 | Analysis of Harmonic Distortion In High Frequency Dielectric Modulated Symmetrical Dual Material Double Gate (SDMDG) For Analog/Rf Circuits | Neha Maurya | 2016 |
| 18 | Analytical Modeling And Performance Analysis Of Junctionless Cylindrical Surrounding Gate MOSFET For Low Power Analog/RF Circuits | Manish Srivastava | 2016 |
| 19 | Dielectric Pocket Dual Material Double Gate (DPDMDG) MOSFET For Enhanced Linearity And Analog/RF Performance | Rachana Chauhan | 2017 |
| 20 | Impact of Oxide Engineering on Analog/RF Performance of Dopingless Si-Ge DMDG MOSFET | Anamika | 2017 |
| 21 | A Low Power Hybrid Full Adder | Monika Yadav | 2017 | B.Tech Students |
| 1 | Junctionless Mosfets For Ultra Low Power Subthreshold Logic Applications | Komal Varshney, Kamlesh Nehra, Amit Singh | 2017 |
| 2 | Comparative Analysis Of 6, 7 And 8 Transistor Sram Memories | Divya Sigtia Chatakala, Lavanya Mayank, Pratap Singh | 2017 |
| 3 | Implementation of Successive Approximation Register A/D Converter Using CMOS | Jyotsna Agrawal, Vinay Singh, Yeeshu Kushwaha, Abhishek Sharma | 2017 |
| 4 | A New Design of A Dual-Edge Triggered Flip-Flop | Arunav Sarkar, Rohit Sahu, Satabdi Mazumder | 2016 |
| 5 | Colour Detection And Face Recognition Using MATLAB And Transmission of Result Over Wireless Module | Utkarsh Jain, Paranjay Sharma, Utkarsh Shrivastava | 2016 |
| 6 | Study Of Image Enhancement Techniques | Shubham Luthra, Kushagra Gupta, Himanshu Kumar Meena | 2016 |
| 7 | Modelling And Simulation Of Channel Potential Of Dgmos Considering S/D Lateral Gaussian Doping Profile | Sanchit Bidwai, Sumeet Meena, Abhishek Shah | 2016 |
| 8 | Interfacing Microcontroller (PIC16F877A) With The GSM Modem To Implement Alarm And Message Alert Based Security System | Shalini Gupta, Soumya Priyadarshini, Jitendra Meena | 2015 |
| 9 | Password Based Logic System | Sandeep Singh, Sanjay Kumar Yadav, Alok Karn | 2015 |
| 10 | Simulation And Optimization Of Devices Using Silvaco | Sanjana Dalela, Shivani Chandra, Valli Palaniappan | 2014 |
| 11 | Design And Development Of Touch Screen Mobile | Arshi Aadil, Anoop Kartikey, Prabhat Ranjan | 2014 |
| 12 | Leakage Current Reduction Techniques And Their Implementation On Vlsi Circuit | Shardool Upadhyay, Piyush Birla | 2013 |
| 13 | Mixed Signal Analysis of CS Based CMOS Circuits | Amrita Singh, Gautam Sharma, Kalpana Meena | 2013 |
| 14 | Design And Implementation of Subthreshold MCML In CMOS Technology | Shatakshi Narayan, Navdha Agrawal, Dewang Tewari | 2013 |
| 15 | Design And Analysis Of Low Power Op-Amp With Enhanced DC Gain | Trilochan Gaur, Saurabh Srivastava, Kundan Kumar | 2012 |
| 16 | Performance Evaluation Of Cs Amplifier With Submicrometer Mosfet In The Sub Threshold Regime Of Operation | Ashish Kumar Niranjan, Gajanan Sahu | 2011 |
| 17 | A Two-Dimensional Subthrshold Surface Potential Model For Dual Material Gate Mosfet | Nimit Jaiswal, Mayuresh Srivastava | 2011 |
| 18 | Implementation Of High Fan-In Logic In High Speed Circuit | Harshit Verma, Manisha Sahi, Rajat Modi | 2010 |